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Assigning a literal to target '%s' bit or subrange results in slower compiled simulation code; 'or' ('and') variable with a mask '1' ('0') value(s) in the bit position(s) that you need to set (clear)

Instead of:
   r_b[15:8]<=8'h00;
use:
   r_b <= r_b & 24'hff00ff;


Assigning target '%s' subrange results in slower simulation code. Use concatenation instead.

Instead of:
   c_x[23:16] = r_a;
   c_x[15:8] = r_b;
   c_x[7:0] = r_c;
use:
   c_x = {r_a, r_b, r_c};

Instead of:
   c_ecc_out_1= cin[29] ^ cin[28] ^ cin[27] ^ cin[26] ^ cin[25] ^ cin[24] ^ cin[23] ^ cin[22] ^ cin[21] ^
                       cin[20] ^ cin[19] ^ cin[18] ^ cin[17] ^ cin[16] ^ cin[15] ^ cin[14] ^ cin[13] ^ cin[12] ^
                       cin[11] ^ cin[7] ^ cin[4] ^ cin[1] ^ cin[0];
use:
   c_ecc_out_l = ^ (c_in & 40'h003ffff893);


Simulation code for shift by constant is not as fast as simulation code for concatenation. Use concatenation instead.

Instead of:
   c_v = c_s << 8; // c_v, c_s are 48 bits wide
use
   c_v = { c_s [39:0], 8'h00 };


출처 : Principles of RTL design_2d