Music is my life

오늘날 대부분의 반도체 IP는 RTL 레벨의 소프트 IP로 공급된다. IP 공급업체들은 기능적으로 정확한 동작을 보장해야 한다. 그럼에도 종종 설계 의도나 구현성, IP 소비자들이 다루어야 할 남은 과제 등에 대한 대화가 간과되기도 한다. 형편없이 설계된 IP는 SoC 레벨에서 타이밍, 루팅 혼잡도, 전력, 클럭 동기화, 테스트 커버리지 등의 실패를 야기할 수 있다. 보통 이러한 문제들은 IP를 SoC에 통합하는데 상당한 노력을 기울인 뒤에야 발견되고는 한다. 그 결과는 설계 재작업, 프로젝트 지연, 그리고 반도체의 실패 등으로 이어진다.

분명 IP 구현성과 품질에 대한 어떤 표준화가 필요하다. 여기서 필자는 그 방법을 제안하고 있다.

Piyush Sancheti, Atrenta Inc
EDA DesignLine

Semiconductor IP reuse can yield a 2x improvement in design productivity for semiconductor companies. However, with these startling productivity gains come integration pain. Why? Semiconductor IP is essentially a black box for the SoC team that comes from various external sources, with varying and often unknown levels of quality and reusability. SoC designers must find a quality metric for semiconductor IP. If not, they may abandon its use.

Most semiconductor IP today is delivered as soft IP - register transfer level (RTL) or configurable generators that produce RTL. IP suppliers do ensure correct functional behavior. Often overlooked in this process is the communication of design intent and implementation feasibility, a task left for the IP consumer to deal with. A poorly designed IP can result in failures at the SoC level with timing, routing congestion, power, clock synchronization, test coverage, etc. Typically these issues will not be uncovered until after a significant engineering effort has been spent on integration of the IP into the SoC and subsequent implementation. The net result is expensive design iterations, project delays and potential silicon failure.

There is clearly the need for some standardization on IP feasibility and quality. Previous efforts in the industry have been unsuccessful for a few reasons:

Lack of measurable design intent for soft IP
An objective and practical measure of IP quality
Lack of automation for 1) and 2)

A solution that overcomes these challenges should benefit the IP supplier who can now explore implementation feasibility at RTL during IP development and ensure quality of the outgoing IP. The SoC designer/integrator, in turn, can use the same information as a programmable IP specification and a quality measure of incoming IP for the purposes of SoC integration and implementation.

I propose an approach for communicating design intent and measuring IP quality that is rooted in how design is done. The general premise is to capture good design practices, known design killers and productivity detractors into a knowledge base that spans coding guidelines, synthesizability, connectivity, portability, interfaces, timing, congestion, power, clocking, testability, etc. This knowledge base should be accumulated over a large sample of existing and new designs, and should continue to evolve as new issues are uncovered. The knowledge can then be deployed in a set of intelligent rules and engines that can detect and analyze such issues for a particular IP. Each such rule can be weighted based on a combination of factors - severity of the issue, likelihood of occurrence, possibility of detection, time to detection and correction, number of downstream tasks impacted (e.g., verification, chip integration, synthesis, place and route, etc.). This approach forms the basis of an "IP Quality Score", a quantifiable measure rooted in actual design. Similarly, design intent can be captured and communicated in the form of target specifications for area, timing, congestion and power, as well as in the form of applicable design waivers or exceptions for that IP.

This bottom-up approach to IP design intent and quality is both practical and evolutionary in nature, since the design knowledge base will continue to evolve with new designs and processes. It yields immediate advantages for both the supplier and the consumer of the IP and the overall semiconductor supply chain.

For the IP supplier, the benefits are:

Target marketing - The design rules and specs can be configured for specific market segments or customers

Objective handoff - A quantified measure of the IP quality based on agreed upon metrics between the supplier and consumer is now possible

Transparency - Visibility into the inherent quality of the IP and programmed communication of design intent is provided

Actionable feedback - The underlying rules and reports can provide the basis of improving the IP Quality Score if required

For the IP consumer, the benefits are:

IP screening - Screen incoming IPs and compare them based on their relative scores

Visibility and risk management - A clear understanding of potential risk areas with the incoming IP which need to be avoided or corrected during implementation

Continuity - The ability to mandate or influence the quality metrics and manage a smooth integration of the IP

I believe that an industry organization should spearhead this IP quality metric effort. Atrenta can and will contribute the automation infrastructure to capture the design rules and also generate IP specs at RTL. The underlying design knowledge comes from the design experts - IP suppliers and SoC experts. Such an industry initiative would also entail collaboration amongst key players in the semiconductor supply chain to enhance the knowledge base eventually lead to true IP quality standardization.

About the Author:
Piyush Sancheti, is Senior Director of Business Development at Atrenta Inc.

< Originally from 09/29/2008 >


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